This invention is directed to silicon on-insulator (SOI) memory elements and in particular, a laser beam recrystallized SOI memory element having multiple gate insulating layers and a method of making the same.
Metal-nitride-oxide-semiconductor (MNOS) memory devices and their silicon gate counterpart (SNOS) devices are well-known non-volatile memory devices capable of storing charges in a thin memory oxide sandwiched between the nitride film and the semiconductor substrate. (Hereafter, MNOS includes SNOS). The conventional process of fabricating a SNOS device typically involves the use of monocrystalline silicon starting material and after forming thick silicon dioxide regions which electrically isolate adjacent devices on the semiconductor chip (typically, by localized oxidation of silicon process) a thin (of the order of about 25 Angstroms) memory oxide film is grown over the gate region by thermal oxidation of the silicon substrate. Another technique of forming the memory oxide is by chemical vapor deposition. Immediately after forming the memory oxide a relatively thick (of the order of 400 Angstroms) silicon nitride is deposited on the oxide film by, for example, low pressure chemical vapor deposition (LPCVD) followed by metal/polysilicon gate formation on the nitride layer.
In the above conventional SNOS process when the memory oxide is formed by thermal oxidation of the silicon substrate, the oxide is invariably not stoichiometric SiO.sub.2 but contains free silicon. Presence of free silicon in the memory oxide deleteriously affects the charge retention characteristic of the memory device. Another disadvantage of forming the memory oxide by thermal oxidation of the silicon substrate is that it is difficult to control the oxide thickness due to high rate of silicon oxidation even at relatively low temperatures. Likewise, when the memory oxide is formed by CVD, the ultra-thin nature (typically 4-5 atoms thick) of the memory oxide necessitates very careful control of the oxide deposition. In addition, both these memory oxide forming techniques present serious difficulties in forming a uniform oxide free of pin holes and other defects. In other words, the prior art technique of forming the SNOS device memory oxide is wrought with lack of oxide integrity and/or the oxide thickness uncertainty. Since the thickness of the memory oxide determines the retention and speed of the device, uncertainty in memory oxide thickness introduces uncertainties in the device characteristics. Yet another disadvantage of the conventional SNOS scheme is the requirement of using a substrate of monolithic silicon material having only single crystals and which has relatively good electrical conductivity, high purity, etc. in order to achieve the necessary high performance (by high operational speed, etc.) of the memory device built thereon. All of these requirements add to the cost of the integrated circuit chip.
The present invention overcomes these and other problems associated with prior art SNOS devices by means of a novel structure and process of making the same.